This frequency counter assignment was performed to utilise the knowledge I learned throughout the year, in EO128 – Digital Electronics. I was required to make use of different TTL compatible components to design a frequency counter circuit; capable of measuring frequencies between 0 and 999 Hz.
Block diagrams, circuit diagrams and simulations will be shown to help explain how a final product was achieved.
This is the frequency input of the counter. The counter is capable of counting a TTL compatible frequency between 0 and 999 Hz. An example frequency input could be a lab function generator, setup accordingly.
The purpose of the counter is to count the number of oscillations or pulses per second on the input. A 74LS90 package has been used as it is capable of counting up to 9, outputting a binary signal which can be processed further into the circuit. These chips can be connected together to count to a value greater than 9. They can also be reset to 0 by pulling R0(1) and R0(2) high.
The latch takes the binary output of the counter and can store it in memory. This is done to allow the counter to count without affecting what is displayed on the 7-segment displays. Whether the latch is storing a value or not is determined by the state of the 1C 2C and 3C 4C pins. The chip used in this circuit is the 74LS75, which incorporates 4 latches in to one package.
Taking the 32.768kHz output from the oscillator crystal, the frequency divider circuit processes the circuit to output a 0.5Hz signal. This is done by using a 4060 chip, which takes the oscillator output and outputs different frequency divisions on each output pin. In the case of this circuit, the ÷16384 output outputs a frequency of 2Hz, when a 32.768kHz oscillator crystal is used. This 2Hz signal is then processed by a 74LS74 dual D-type flip-flop, wired up to output a 0.5Hz signal; which can be used by the counter and latch reset pins.
Because the counter and latch reset pins behave differently when a signal is high or low, a 74LS04 NOT-gate has been used to invert the 0.5Hz signal before the latch ICs, so that they behave correctly. Two NOT-gates from the same 74LS04 package have also been used to process the oscillator crystal output, before inputting the signal into the 4060 frequency divider chip.
The 74LS47 BCD to 7-segment display drivers take the binary input from the latch and convert the signal into an output that displays the corresponding digit on the 7-segment display. These display drivers are designed to drive Common Anode displays. Alternatively, 74LS48 chips could have been used if Common Cathode displays were to be used. These display driver chips are straight-forward to use and only require the lamp test and ripple-blanking input/outputs to be wired correctly, according to the truth table on the datasheet.
In the final circuit, 57-0128 7-segment displays were used, but any common anode 7-segment display would work with this circuit, providing the pin-out of the display being used was observed.
The circuit was designed and simulated in Multisim. Below is a screenshot of the Multisim file, running a simulation with an input frequency of 123Hz:
Because Multisim doesn’t correctly simulate oscillator crystals, the oscillator and frequency divider circuits were replaced with a software function generator, for the purpose of simulation.
Once a simulation was working, the oscillator crystal circuit and frequency divider was tested on a breadboard. When it was confirmed that each part of the circuit would work together, the PCB was designed.
The schematic was transferred over to Proteus and a PCB was designed and printed. Below are some pictures of the PCB design and finished, working frequency counter PCB. Among the pictures is a picture of the custom cable used to connect the PCB to the power supply and function generator.
Although this frequency counter works perfectly well, a couple of improvements could be made:
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